The present invention is directed to methods for evaluating device models in circuit simulators. Circuit simulators are computer programs that solve a system of mathematical expressions, such as algebraic differential equations, that describe or model a circuit. Simulators may construct the mathematical expressions, such as algebraic differential equations, from physical or analytical models of devices contained in the circuit. A physical or analytical model is basically a set of equations that express, for example, device currents and charges (or capacitances) as functions of the terminal voltages. A physical or analytical model may be employed to evaluate other parameters as well.
Sometimes weeks of computation are required to carry out a proper simulation of a complex circuit. It has been observed that simulators may spend a majority of the computation time (e.g., approximately 70%) in constructing the circuit equations (i.e., evaluating device models) rather than solving the equations. Another difficulty with such purely mathematical modeling is that it is often difficult and time consuming to extract a good model for a complex device or circuit.
One way to reduce the processor time required for device model evaluation is to replace the physical or mathematical model with a table model. In a table model, measured or precomputed device parameters, such as currents, capacitances or charges, are stored for different bias voltage points in a tabular form. Interpolation is employed for determining bias voltage values that do not coincide with value entries.
Some table models are based upon structured grids. Structured grids are characterized by regular connectivity. With structured regular connectivity, the points of the grids can be indexed and the neighbors of each point can be calculated rather than looked up. For example, in a structured grid the neighbors of a point (i,j) are located at (i+1,j), (i−1,j), and so on. Some desirable properties for device models, such as continuity and monotonicity, can be preserved in structured grid systems if proper interpolation schemes are employed. However, one drawback of a structured grid system is that its accuracy is limited by the available computer memory, especially as the number of dimensions increases.
Other table models may be based upon unstructured grids. An example of such an unstructured grid table model employs a tree-based model approximation (TBMA) method. TBMA is a method to split the root partition, which is the function domain of interest, recursively. The function domain is partitioned continuously until the difference between the actual functional values and the interpolated values in all partitions meet specified error or tolerance criteria. When the error inside one partition is less than the specified tolerance, the division of that partition is stopped but division of the other partitions is continued unless they meet the error or tolerance criteria also. As a result, smaller partitions appear at regions of the domain where the function is more nonlinear. On the other hand, if the function is approximately linear large partitions will be sufficient to give the required accuracy. The divided function domain is represented by a modified 2N tree where N is the dimension of the function domain. A 2N tree is a tree in which each interior node has exactly 2N descendants, each of which represents a partition of the function domain.
An example of an unstructured grid device model is described in “Device Model Approximation Using 2N Trees”, by David M. Lewis; IEEE Transactions on Computer-Aided Designs, Vol. 9, No. 1; January 1990. Lewis describes an application of 2N trees to device model approximation in which the domain of the device model functions is partitioned using a modified 2N tree with smaller partitions where the function is more nonlinear. An application of Lewis' approach is described for approximating MOSFET models by Cheng and Li in “A Fast Method for MOS Model Evaluation in VLSI Simulation with Controllable Error”, China 1991 International Conference on Circuits and Systems; June 1991. An application of Lewis' approach is described for approximating SOI transistor models by Nadzhin et al. in “SOI Transistor Model for Fast Transient Simulation”, ICCAD '03; Nov. 11-13, 2003.
Lewis describes partitioning a domain into accuracy partitions to preserve accuracy of modeling using the table embodied in the grid. Then Lewis describes a complex procedure involving evaluation of constraints to further partition the domain for purposes of preserving continuity of the table model.
There is a need for a simpler, more straightforward approach to establishing a table model approximation for evaluating a complex device.
There is a need for a table model approximation method for evaluating a device that preserves the monotonicity and continuity of a model while reducing computation time for model evaluation.